Please use this identifier to cite or link to this item:
http://hdl.handle.net/10263/6214| Title: | Floorplan equipartitioning using staircase channel minimizing the crossing nets |
| Authors: | Chattopadhyay, Nirmalya |
| Keywords: | VLSI floorplan Staircase channel Crossing nets Algorithms |
| Issue Date: | 1997 |
| Publisher: | Indian Statistical Institute, Kolkata |
| Citation: | 43p. |
| Series/Report no.: | Dissertation;97-41 |
| Description: | Dissertation under the supervision of Dr. Subhas C. Nandy |
| URI: | http://hdl.handle.net/10263/6214 |
| Appears in Collections: | Dissertations - M Tech (CS) |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| DISS-41.PDF | Dissertation is the original PDF | 668.77 kB | Adobe PDF | View/Open |
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