Please use this identifier to cite or link to this item: http://hdl.handle.net/10263/6216
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dc.contributor.authorMani, J V S-
dc.date.accessioned2016-06-30T21:11:52Z-
dc.date.available2016-06-30T21:11:52Z-
dc.date.issued1997-
dc.identifier.citation36p.en_US
dc.identifier.urihttp://hdl.handle.net/10263/6216-
dc.descriptionDissertation under the supervision of Dr. Bhargab B. Bhattacharyaen_US
dc.language.isoenen_US
dc.publisherIndian Statistical Institute, Kolkataen_US
dc.relation.ispartofseriesDissertation;97-43-
dc.subjectCombinational circuiten_US
dc.subjectFalse pathen_US
dc.subjectPath problemsen_US
dc.titleGeneral false path problem in timing analysis of combinational circuitsen_US
dc.typeThesisen_US
Appears in Collections:Dissertations - M Tech (CS)

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