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Please use this identifier to cite or link to this item: http://hdl.handle.net/10263/6226
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dc.contributor.authorBhattacharjee, Subhasis-
dc.date.accessioned2016-07-01T15:44:26Z-
dc.date.available2016-07-01T15:44:26Z-
dc.date.issued1998-
dc.identifier.citation33p.en_US
dc.identifier.urihttp://hdl.handle.net/10263/6226-
dc.descriptionDissertation under the supervision of Prof. B.P. Sinha, ACM Uniten_US
dc.language.isoenen_US
dc.publisherIndian Statistical Institute, Kolkataen_US
dc.relation.ispartofseriesDissertation;98-53-
dc.subjectRedundant radix-4en_US
dc.subjectBinary number systemen_US
dc.subjectArithmetic operationsen_US
dc.subjectLogical operationsen_US
dc.subjectFPGA modulesen_US
dc.titleDesign and implementation of a redundant radix-4 coprocessor with binary interfaceen_US
dc.typeThesisen_US
Appears in Collections:Dissertations - M Tech (CS)

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