Please use this identifier to cite or link to this item:
http://hdl.handle.net/10263/6234| Title: | Effect of circuit structure on path delay fault testability in VLSI design |
| Authors: | Sarkar, Biplab |
| Keywords: | Design for testability Path model Testability preserving transformations Testability improving transformations |
| Issue Date: | 1998 |
| Publisher: | Indian Statistical Institute, Kolkata |
| Citation: | 24p. |
| Series/Report no.: | Dissertation;98-61 |
| Description: | Dissertation under the supervision of Prof. Bhargab B. Bhattacharya, ACM Unit |
| URI: | http://hdl.handle.net/10263/6234 |
| Appears in Collections: | Dissertations - M Tech (CS) |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| DISS-61.PDF | Dissertation is the original PDF | 1.63 MB | Adobe PDF | View/Open |
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