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Please use this identifier to cite or link to this item: http://hdl.handle.net/10263/6234
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dc.contributor.authorSarkar, Biplab-
dc.date.accessioned2016-07-01T17:29:14Z-
dc.date.available2016-07-01T17:29:14Z-
dc.date.issued1998-
dc.identifier.citation24p.en_US
dc.identifier.urihttp://hdl.handle.net/10263/6234-
dc.descriptionDissertation under the supervision of Prof. Bhargab B. Bhattacharya, ACM Uniten_US
dc.language.isoenen_US
dc.publisherIndian Statistical Institute, Kolkataen_US
dc.relation.ispartofseriesDissertation;98-61-
dc.subjectDesign for testabilityen_US
dc.subjectPath modelen_US
dc.subjectTestability preserving transformationsen_US
dc.subjectTestability improving transformationsen_US
dc.titleEffect of circuit structure on path delay fault testability in VLSI designen_US
dc.typeThesisen_US
Appears in Collections:Dissertations - M Tech (CS)

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