Please use this identifier to cite or link to this item:
http://hdl.handle.net/10263/6256
Title: | Algorithm for mapping boolean network to LUT based FPGAs |
Authors: | Bhattacharyya, Jayasri |
Keywords: | FPGA DAG-map algorithms Boolean network Mapping |
Issue Date: | 2001 |
Publisher: | Indian Statistical Institute, Kolkata |
Citation: | 47p. |
Series/Report no.: | Dissertation;2001-84 |
Description: | Dissertation under the supervision of Dr. Sushmita Sur-Kolay |
URI: | http://hdl.handle.net/10263/6256 |
Appears in Collections: | Dissertations - M Tech (CS) |
Files in This Item:
File | Description | Size | Format | |
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DISS-84.PDF | Dissertation is the original PDF | 3.27 MB | Adobe PDF | View/Open |
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