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Please use this identifier to cite or link to this item: http://hdl.handle.net/10263/6256
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dc.contributor.authorBhattacharyya, Jayasri-
dc.date.accessioned2016-07-01T21:36:48Z-
dc.date.available2016-07-01T21:36:48Z-
dc.date.issued2001-
dc.identifier.citation47p.en_US
dc.identifier.urihttp://hdl.handle.net/10263/6256-
dc.descriptionDissertation under the supervision of Dr. Sushmita Sur-Kolayen_US
dc.language.isoenen_US
dc.publisherIndian Statistical Institute, Kolkataen_US
dc.relation.ispartofseriesDissertation;2001-84-
dc.subjectFPGAen_US
dc.subjectDAG-map algorithmsen_US
dc.subjectBoolean networken_US
dc.subjectMappingen_US
dc.titleAlgorithm for mapping boolean network to LUT based FPGAsen_US
dc.typeThesisen_US
Appears in Collections:Dissertations - M Tech (CS)

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