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Please use this identifier to cite or link to this item: http://hdl.handle.net/10263/6292
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dc.contributor.authorSrivastava, Praveen-
dc.date.accessioned2016-07-04T20:38:20Z-
dc.date.available2016-07-04T20:38:20Z-
dc.date.issued2004-
dc.identifier.citation35p.en_US
dc.identifier.urihttp://hdl.handle.net/10263/6292-
dc.descriptionDissertation under the supervision of Prof. Bhargab B. Bhattacharyaen_US
dc.language.isoenen_US
dc.publisherIndian Statistical Institute, Kolkataen_US
dc.relation.ispartofseriesDissertation;2004-122-
dc.subjectScan designen_US
dc.subjectScan architectureen_US
dc.subjectDTSen_US
dc.subjectLow power testingen_US
dc.titleScan path architecture for low power testingen_US
dc.typeThesisen_US
Appears in Collections:Dissertations - M Tech (CS)

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