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Please use this identifier to cite or link to this item: http://hdl.handle.net/10263/6364
Title: General recursive staircase bipartition scheme for VLSI floor plan layout with simultaneous minimization of net crossovers
Authors: Bag, Amlan
Keywords: VLSI bipartition
Staircase channel
Buffer insertion
Floorplan
Issue Date: 2007
Publisher: Indian Statistical Institute, Kolkata
Citation: 38p.
Series/Report no.: Dissertation;2007-200
Description: Dissertation under the supervision of Prof. Bhargab B. Bhattacharya
URI: http://hdl.handle.net/10263/6364
Appears in Collections:Dissertations - M Tech (CS)

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