Effect of circuit structure on path delay fault testability in VLSI design
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Date
1998
Authors
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Journal ISSN
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Publisher
Indian Statistical Institute, Kolkata
Abstract
Description
Dissertation under the supervision of Prof. Bhargab B. Bhattacharya, ACM Unit
Keywords
Design for testability, Path model, Testability preserving transformations, Testability improving transformations
Citation
24p.