General recursive staircase bipartition scheme for VLSI floor plan layout with simultaneous minimization of net crossovers
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Date
2007
Authors
Journal Title
Journal ISSN
Volume Title
Publisher
Indian Statistical Institute, Kolkata
Abstract
Description
Dissertation under the supervision of Prof. Bhargab B. Bhattacharya
Keywords
VLSI bipartition, Staircase channel, Buffer insertion, Floorplan
Citation
38p.