Testing and simulation involved in the circuit design
| dc.contributor.author | Nayagam N, Gomathi | |
| dc.date.accessioned | 2016-06-30T17:34:08Z | |
| dc.date.available | 2016-06-30T17:34:08Z | |
| dc.date.issued | 1996 | |
| dc.description | Dissertation under the supervision of Dr. Bhargab Bhattacharya | en_US |
| dc.identifier.citation | 65p. | en_US |
| dc.identifier.uri | http://hdl.handle.net/10263/6199 | |
| dc.language.iso | en | en_US |
| dc.publisher | Indian Statistical Institute, Kolkata | en_US |
| dc.relation.ispartofseries | Dissertation;96-24 | |
| dc.subject | VLSI design cycle | en_US |
| dc.subject | Circuit design | en_US |
| dc.subject | Logic synthesis | en_US |
| dc.title | Testing and simulation involved in the circuit design | en_US |
| dc.type | Thesis | en_US |
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