Dynamic Property Ordering for Efficient Multi-Property Bounded Model Checking

Abstract

Formal verification plays a critical role in ensuring the correctness of modern hardware designs. As the complexity of digital systems increases, designs are often associated with a large number of verification properties that must be analyzed within limited computational resources. In conventional multi-property bounded model checking (BMC), all properties are verified simultaneously. While this approach enables parallel analysis, difficult properties can consume a disproportionate amount of resources, causing simpler properties to be delayed and reducing the overall efficiency of bug detection. This thesis presents dynamic property ordering techniques for efficient multi-property verification using SAT-based bounded model checking in the ABC verification framework. The central idea is to verify properties individually and dynamically prioritize them based on their observed verification progress, allowing computational resources to be directed toward properties that are more likely to yield results within a given time budget.Two dynamic property ordering algorithms are proposed. The first algorithm, ALG1, employs a round-robin style strategy in which unsolved properties are periodically reordered according to the maximum verification depth (frame) reached, prioritizing properties that demonstrate greater progress. The second algorithm, ALG2, adopts a priority-based scheduling approach where each property’s priority is determined by its verification rate, measured as frames explored per second. Properties with higher progress rates are allocated greater verification resources. The proposed approaches are evaluated on benchmark suites from the Hardware Model Checking Competition (HWMCC) 2012 and 2013 and compared against two baselines: the conventional ABC multi-property verification method and an Equal Time Bounding (ETB) strategy that distributes the available verification time equally among all properties. Experimental results demonstrate that dynamic property ordering significantly improves verification efficiency. Both ALG1 and ALG2 solve more properties and achieve greater verification depth within the same time budget, while also accelerating bug discovery. Across the benchmark set, the proposed methods provide improvements exceeding 40% over the baseline approaches in key performance metrics. The results demonstrate that dynamic property scheduling is an effective technique for improving the scalability and effectiveness of multi-property bounded model checking, offering a practical solution for faster bug detection and enhanced utilization of verification resources.