Parallel system design for time delay neural networks

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dc.contributor.authorChang, David
dc.contributor.authorPal, Sankar K
dc.date.accessioned2012-05-08T15:52:48Z
dc.date.available2012-05-08T15:52:48Z
dc.date.issued2000
dc.identifier.citationIEEE Transaction system man and cybernetics,Pt-C ,Application and reviews,V30,P265-275en_US
dc.identifier.urihttp://hdl.handle.net/10263/3877
dc.language.isoenen_US
dc.subjectParallel computingen_US
dc.subjectPipeline architectureen_US
dc.subjectTime delay neural networken_US
dc.subjectSpeech recognitionen_US
dc.titleParallel system design for time delay neural networksen_US
dc.typeArticleen_US

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