Effect of circuit structure on path delay fault testability in VLSI design

Sarkar, Biplab2016-07-012016-07-01199824p.http://hdl.handle.net/10263/6234Dissertation under the supervision of Prof. Bhargab B. Bhattacharya, ACM UnitenDesign for testabilityPath modelTestability preserving transformationsTestability improving transformationsEffect of circuit structure on path delay fault testability in VLSI designThesis