Synthesis of symmetric functions for path delay fault testability

Chakrabarti, SDas, SDas, D KBhattacharya, Bhargab B2012-05-072012-05-072000IEEE Transaction on CAD,V19,P1076-1081http://hdl.handle.net/10263/3853enDelay faultSymmetric boolean functionSynthesis for testibilitySynthesis of symmetric functions for path delay fault testabilityArticle