Bhattacharya, Bhargab B2013-06-142013-06-141989IEEE Transactions on Computers,v.38 ,no.11 ,p.1580-1584http://hdl.handle.net/10263/5433enParity testableCombinational circuitMaximal supergatesSingle external test-mode pinDesign of parity testable combinational circuitsArticle