De, MallikaSinha, Bhabani P2013-05-072013-05-071994-05IEEETOC, v 43, no 5, p 603-607http://hdl.handle.net/10263/5351enBalanced ternary logicColumn compressionPrecarry additionSystolic architectureTernary multiplicationFast parallel algorithm for ternary multiplication using multivalued IL technologyArticle