General recursive staircase bipartition scheme for VLSI floor plan layout with simultaneous minimization of net crossovers

Bag, Amlan2016-07-062016-07-06200738p.http://hdl.handle.net/10263/6364Dissertation under the supervision of Prof. Bhargab B. BhattacharyaenVLSI bipartitionStaircase channelBuffer insertionFloorplanGeneral recursive staircase bipartition scheme for VLSI floor plan layout with simultaneous minimization of net crossoversThesis