Design and implementation of a redundant radix-4 coprocessor with binary interface
| dc.contributor.author | Bhattacharjee, Subhasis | |
| dc.date.accessioned | 2016-07-01T15:44:26Z | |
| dc.date.available | 2016-07-01T15:44:26Z | |
| dc.date.issued | 1998 | |
| dc.description | Dissertation under the supervision of Prof. B.P. Sinha, ACM Unit | en_US |
| dc.identifier.citation | 33p. | en_US |
| dc.identifier.uri | http://hdl.handle.net/10263/6226 | |
| dc.language.iso | en | en_US |
| dc.publisher | Indian Statistical Institute, Kolkata | en_US |
| dc.relation.ispartofseries | Dissertation;98-53 | |
| dc.subject | Redundant radix-4 | en_US |
| dc.subject | Binary number system | en_US |
| dc.subject | Arithmetic operations | en_US |
| dc.subject | Logical operations | en_US |
| dc.subject | FPGA modules | en_US |
| dc.title | Design and implementation of a redundant radix-4 coprocessor with binary interface | en_US |
| dc.type | Thesis | en_US |
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